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For half a century, the semiconductor industry is moving rapidly, according to the Moor Act of the Devil, process, architecture, and technology are rebuilt, but it is a changing process. In recent years, the semiconductor industry has done a great deal of effort and has not been able to disrupt or win many old roads, and new ideas and new proposals have to be developed.
For instance, processor chip packaging has been used in the past to propagate a large cake on a large carpet. With the diversity of integral modules and complexity of process technologies, it is more difficult to maintain a traditional system and 3D stereo is essential to the world.
In fact, the 3D stacked chip design, not everyone stranger, many chips are being tested, and some have developed very matured. NAND is a flash memory, 3D stacked package has achieved an amazing 96 layers, which will continue to increase in the future, regardless of the capacity or cost more can be arbitrarily.
However, based on the Core CPU processor, due to various factors, the packaging method was not very important, it turned black on a flat substrate or single chip, or multi-chip integration. .
Recently, Intel introduced Revolutionary Forrest 3D Stereo Chip Packaging Technology, a 3D stacked design for a CPU processor. This will be an important step in the history of stimulation of product upgrade or the history of CPU processors.
The Intel Foveros 3D packaging technology has great advantages for 3D stacking, enabling logical on logical integration as chip design has a great flexibility.
Technology IP components, various memory and I / O components are used for different processes and architectures for new device formats.Smaller partnerships were created to produce a special display, independent modules, and a product to achieve low cost or high cost before fulfilling the form factor design requirements, various applications, power consumption. Suitable performance.
In fact, before the introduction of 2D Integration Technology "IBB" (embedded multi-chip interconnect bridge), it is much more than traditional 2D single-chip design to combine input modules into a single package for different processes and functions. A product representative is a Kabie Lake-G series that helps the market to improve yield, improve overall performance, reduce costs and slow down. It includes the Intel eight-generation General Core CPU, AMD Vega GPU Graphics Core.
Combining the advantages of the 2D integration, combining density, flexibility and new level logic chips can completely suppress and rebuild the system chip architecture.
In the diagram of the Fairs 3D 3D Stack package provided by Intel you can see the insight of the cover design.
At the bottom of the package is the basic computing chip kernel, then you need those of computing, vision, and other components, high performance logic, low power logic, high density memory, high speed memory, sensors, power controls, radio or optoelectronics, -Party IP depends on whether it is handy Users, users can customize to their needs.
of course,From
How to maintain high-speed interaction between different factors to ensure overall performance, energy consumption and top quality, and certainly the design capacity and technical strengthTSV TSV and Discreet Integrated Circuits are key.
Intel emphasized itFrom
3D packaging costs may not be less, but it does not pay attention, but it is the most suitable IP in the most appropriate location for mash, which is the real driving force.
The second half of 2019 will appear in a series of forex 3D packaging technologies, which will become a major base for future Intel chip designs.
"Loughfield" is the first product of the world's first hybrid CPU architecture product.Intel also showed a small reference multiprocessor based on processor. This is oem.
The lowfield power 22nm FFL Bait Silicone combines high quality 10nm computational stats chiplet, the first zip processor, GPU core graphics card, memory controller and image processing unit. Display engine, along with many I / O input, output, debugging and control modules.
As a hybrid x86 architecture product, the 10nm processor has a 10nm high sunny call CPU core (using ice laser processor), and a 10nm process with four low-power stable CPU cores. The last level cache is shared, like the IC Lack, the 11th generation of the core graphic card was developed and not only 64 implementation units but also the power consumption.
In addition to the advanced design feature, it is much more exciting, expecting its ultra-short size and intensity energy consumption.
According to official figures,From
Luxe's package size is now 12 x 12 mm. Multiple coverage design is a multiple coverage coverage. Multiple reference designs are designed to be the lowest motherboards in Intel's history. It meets the needs of 11-inch screen sized devices..
Power consumption, according to Intel's previous statement,From
If Lakefield is on standby, it is only up to 0.002W, which is almost reserved, and no maximum power consumption may exceed 7W.Using a fan is completely unnecessary. The natural energy density is lightweight and thin.
The chip design moves from 2 to tile to 3D stacking, providing high quality, high density and low energy chip processing technology that provide a robust base for converting devices and systems, and open up a new dimension to the development and development of the semiconductor industry. The door with more ideas to explore.
Future's 3D packaging technology demonstrates the full range of future chip designs that Intel has adopted a new direction, more powerful, more powerful, less powerful, more useful apps designed no more than traditional conventional frameworks. Different products to meet different tools and market needs.
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